Trading Speed and Power for Reduced Substrate Noise from Digital CMOS Circuits
نویسندگان
چکیده
In a mixed analogue/digital system, the statechanges of digital circuits generate switching noise that is transferred through the substrate and the power-lines to sensitive analogue nodes. This work investigates how trade-offs with speed and power consumption can be used to decrease this substrate noise. Six different digital CMOS design techniques have been simulated and compared with respect to their trade-off possibilities. The simulations result show how speed and power can be traded for lower digital switching noise by selecting a suitable design technique and power supply voltage.
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